Versatile interconnection bus

A bus arbitration system comprising a plurality of bus lines and a clock which produces first and second phrases in which a drive generates a first logic state during the first phase to precharge the capacitance associated with the bus lines and generates either first or second logic state during th...

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Bibliographische Detailangaben
Hauptverfasser:	BENNETT, DONALD B, THORSRUD, LEE T, PETSCHAUER, THOMAS W
Format:	Patent
Sprache:	eng
Schlagworte:	BLASTING CALCULATING COMBUSTION ENGINES COMBUSTION ENGINES IN GENERAL COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING HEATING HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS INTERNAL-COMBUSTION PISTON ENGINES LIGHTING MECHANICAL ENGINEERING PHYSICS WEAPONS
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Beschreibung
Zusammenfassung:	A bus arbitration system comprising a plurality of bus lines and a clock which produces first and second phrases in which a drive generates a first logic state during the first phase to precharge the capacitance associated with the bus lines and generates either first or second logic state during the second phase. Also, a bus interface is described in which different types of information are transmitted during different phases.