Electronic communication clocking mechanism

Apparatus for providing a relatively constant clocking signal to a serial input/output device from a microprocessor regardless of whether the microprocessor is executing a normal instruction cycle or an extended cycle. A state machine is driven by the same clock which drives the microprocessor and a signal from the microprocessor indicating the presence of a normal or extended instruction cycle. The state machine and the clock which drives the microprocessor drive a clocking circuit which produces a first waveform if a normal instruction cycle is being executed, and a second waveform if an extended instruction cycle is being executed. Both waveforms are edge synchronized to the clock which drives the microprocessor.