Minimal mask process for fabricating a lateral insulated gate semiconductor device
An eight mask process for forming a lateral insulated gate semiconductor device is disclosed. The gate structure can be used as a mask to align the third and fifth regions of the device and a third protective layer aligns the fourth and sixth regions of the device.
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | An eight mask process for forming a lateral insulated gate semiconductor device is disclosed. The gate structure can be used as a mask to align the third and fifth regions of the device and a third protective layer aligns the fourth and sixth regions of the device. |
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