High speed equalization in a memory

A memory is comprised of memory cells located at intersections of word lines and bit line pairs. The memory has a read mode in which data is read from a bit line pair selected by a column address. The data to be read is provided to bit line pairs by the memory cells which are coupled to a word line which has been selected to be enabled by a row address. In the write mode, data is written to a memory cell which is coupled to an enabled word line and which is coupled to a bit line pair into which data has been selected to be written. The pairs of bit lines are equalized in voltage in response to not only an address transition but also in response to a transition from the write mode to the read mode.