Dynamically configurable fast Fourier transform butterfly circuit

A decimation-in-frequency fast-Fourier-transform butterfly circuit for performing a radix-four butterfly operation includes a first group of adders (86, 88, 90, and 92), a second group of adders (70, 72, 74, and 76), and a group of twiddle-factor multipliers (78, 80, and 82) that are interconnected in such a way as to perform the radix-four fast-Fourier-transform algorithm. Additionally, bypass lines (102, 104, 106, and 108) bypass the first group of adders, and switches (94, 96, 98, and 100) switch between the signals on the bypass lines and those from the first group of adders. As a result, the circuit performs a radix-four FFT operation when the switches are in one state, and it performs two radix-two FFT butterfly operations simultaneously when the switches are in the other state.