Variable segment size plural cache system with cache memory unit selection based on relative priorities of accessed encached programs

Variable segment size plural cache system with cache memory unit selection based on relative priorities of accessed encached programs

A cache memory control system has a segment descriptor with a 1-bit cache memory unit designation field, and a register for storing data representing the cache memory unit designation field. An output from the register is supplied to one cache memory unit, whereas inverted data of the output from th...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: BANNAI, AKIRA, SUZUKI, SHOHEI
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A cache memory control system has a segment descriptor with a 1-bit cache memory unit designation field, and a register for storing data representing the cache memory unit designation field. An output from the register is supplied to one cache memory unit, whereas inverted data of the output from the register is supplied to the other cache memory unit.