Column decoder circuit for use with memory using multiplexed row and column address lines
A memory having multiplexed address inputs uses a column decoder which is deactivated during row address time and becomes activated during column address time. Access time and power dissipation are reduced since the column decoder need not be fully recovered after row address information has termina...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A memory having multiplexed address inputs uses a column decoder which is deactivated during row address time and becomes activated during column address time. Access time and power dissipation are reduced since the column decoder need not be fully recovered after row address information has terminated and column address information is available. |
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