Method of making substrate injection logic operator structure

An SFL operator and process for its manufacture. The operator is manufactured from a low-doped P-type substrate on which are successively implanted a highly-doped P-type layer and a highly-doped N-type layer. Below a metallic collector contact of the NPN transistor of the SFL operator, the structure successively comprises an epitaxial N-layer, an average-doped R-type layer and a highly-doped N-type layer. This structure is compatible with the manufacturing on the same silicon chip of both SFL operators and classical linear bipolar transistors.