Signal equalization in quadrilinear imaging CCD arrays

In the operation of a high density quadrilinear CCD imaging array, photogenerate charge is transferred from the photosites, transversely through one inner CCD register to a second outer CCD register, before clocking the CCD registers. During the transfer from the inner to the outer registers, the signal charge passes through a region defined by boundaries spaced relatively widely to a region in which the boundaries are required to be spaced closely. In the latter region, two dimensional fringing fields from the boundaries elevate the minimum potential which defines the signal charge path and creates a potential step which traps a significant percentage of the signal charge. This trapping creates a large offset between the output signals from the inner and outer register. The concept proposed is to use a fat zero, i.e., an intentionally introduced small packet of charge, injected into the input of both the inner and outer CCD registers in order to totally eliminate the offset. The input structure for fat zero injection would be designed so that the size of the fat zero would be determined by the same factors creating the potential step, thereby totally eliminating any charge loss from the signal packet during the initial transfer from the photosites, and eliminating any dependance on processing variations.