Electrically programmable and erasable memory cell

Electrically programmable and erasable memory cell

An electrically programmable and eraseable memory cell in which charge carriers are tunnelled between a floating gate and a drain region in the substrate through a thin oxide tunnel region, the borders of said tunnel region being confined to a small area well inside the borders of both the drain reg...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: PRIEL, URY, YARON, GIORA, PRASAD, JAYASIMHA S, SHUM, YING K, EBEL, MARK S
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:An electrically programmable and eraseable memory cell in which charge carriers are tunnelled between a floating gate and a drain region in the substrate through a thin oxide tunnel region, the borders of said tunnel region being confined to a small area well inside the borders of both the drain region and the floating gate. Dual paths are utilized to connect the tunnel region of the gate to the memory cell region of the gate.