Self-aligned all-n+ polysilicon CMOS process

Disclosed is a process for forming self-aligned all n+-doped polysilicon gates and interconnections in CMOS integrated circuits. Polysilicon is formed into the n-FET gate, a barrier for the p-FET region and the interconnect pattern. Then, arsenosilicate glass (ASG) is formed over the interconnect and the p-FET gate and N-FET active regions. The p-FET gate is etched using the ASG as a mask. The device is heated driving in impurities from the ASG to n+ dope the polysilicon and form the n-FET source and drain. Then, boron is implanted in the p-FET source and drain regions.