Digitally adjustable phase shifting circuit

A counter produces, as a function of time, an M bit count of cycles of a periodic signal. A storage device stores a changeable value represented by N bits comprising M higher order bits and N-M lower order bits. An adder produces M bits corresponding to the sum of M counter bits and M higher order bits. A digital-to-analog converter produces an alternating signal corresponding to the value of the M summed bits and N-M lower order bits where the phase of the alternating signal relative to an arbitrary reference signal corresponds to the value stored in the storage device.