Integrated logic gate with NPN inverter, PNP clamp, coupling, Shottky diodes and diffused crossunder

A logic element structure suitable for high density integration including a vertical NPN transistor, a lateral PNP anti-saturation transistor, and a Schottky diode coupled to the collector of the NPN transistor and providing a logic element output. The logic element structure is fabricated as a monolithic integration on a semiconductor crystal and comprises an isolated region of N-type semiconductor material bounded on its inner principal face by a substrate and by a buried layer of N+ type material, the isolated region being further bounded on its lateral faces by an insulating wall of P-type semiconductor material and on its principal outer face by a first region of P-type semiconductor material, this first region of P-type semiconductor material at the periphery of the isolated region and partially covering the insulating wall, the isolated region being further bounded on its principal outer face by a second region of P-type semiconductor material insulated from the first region of P-type semiconductor material by a minimum thickness of N-type semiconductor material, this second region of P-type semiconductor material surrounding a second region of N+-type semiconductor material, the Schottky diode formed by a metallization on the principal outer face of the isolated region between the first and second P-type semiconductor regions.