Sense amplifier with dual parallel driver transistors in MOS random access memory

A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with a bistable sense amplifier circuit at the center of each column. Instead of a single pair of cross-coupled driver transistors forming the bistable circuit, dual parallel pairs are used. One pair used in the initial sensing has a long channel length so that the pair may be more readily matched, while the other pair used later in the cycle for driving the zero-going side of the column line to ground has a shorter channel to enhance speed.