Programmable logic arrays

A programmable logic array (PLA) is provided with a plurality of storage registers. The PLA includes an AND matrix which generates inputs to an OR matrix which in turn selectively feeds output signals into the storage registers. At a selected time, a selected storage register provides the output signals of the PLA and/or feedback signals to the AND array so that sequential logic functions can be performed in the PLA. The plurality of storage registers are used to store various combinations of the OR matrix output signals. A decoder permits selection of one of the registers at a time to allow time discrimination among the various stored combinations of the OR matrix output signals for the purposes of feeding them out of the PLA and/or feeding them back into the AND matrix.