Interface linking synchronous sense and drive matrices of telephone system with a processor of signalization data

Sensors SE and drivers AT electrically linked to various points of communication equipment, e.g. in a telephone system, are periodically explored by an interface linking them with a processor, under the control of a time base successively reading out their addresses during synchronous phases of respective time slots of a recurrent frame also having other phases set aside for the asynchronous exchange of data with the processor. The interface comprises a first and a second read/write memory ME1, ME2 respectively storing information relating to the evaluation of incoming signals from the sensors and to the sending of outgoing signals to the drivers, the contents of these memories being updated from time to time during asynchronous phases allocated to communication with the processor. The evaluation of incoming signals is performed in a first logic network IN, with the aid of integrating circuitry including a read-only memory ROM1 inserted in a feedback loop of the incoming-signal memory ME1; the forwarding of change-of-state signals from this logic network IN to the processor may be inhibited in selected instances by masking criteria stored in the incoming-signal memory ME1 which can be modified, on instructions received from the processor, with the aid of a second logic network LM including another read-only memory ROM3 also inserted in a feedback loop of memory ME1.