Data processing interrupt apparatus having selective suppression control

Interrupts generated within a data processor (internal interrupts) and an interrupt received from a peripheral device (external interrupts) coupled with the processor are prioritized and, unless suppressed, are coupled to generate an interrupt signal for use in addressing a routine for servicing the particular highest priority requesting internal or external interrupt. All further interrupts are suppressed during the time required to service the interrupt and, depending upon the type of interrupt, either the internal or external interrupt may be suppressed for one or two instruction times for debug purposes or under computer program control as required for a particular operation.