Transparent tri state latch

Tri state logic gates in series are disclosed for permitting the latching of information from a first circuit by enabling a second circuit at the time information from the first circuit becomes valid. At the start of the memory cycle the second circuit is disabled and the first circuit is enabled. The data in the memory will appear at the output of the memory circuit to be delivered to the computer. Data is latched and retained on the data output bus by enabling the second circuit which assumes the level that appears on its input when enabled. The first circuit may then be disabled to permit it to carry out other operations.