Regenerator circuit

The problem of gradual dissipation of charge in charge packets in charge-coupled devices (CCDs) as the packets are successively shifted is overcome by a regenerator circuit which also provides a basic structure for effecting elemental logic and arithmetic functions. A standardized charge packet is injected along with a digitally valued but somewhat diminished charge packet into a potential well under a storage electrode arranged to retain a single charge packet. Overflow from the storage electrode region that represents only some part of a full charge packet is detected by a master sensing gate that controls a slave gate forming a shunt path for the full charge packet and that is normally maintained in a transfer state. The slave gate shifts to a barrier state when the overflow packet is present, however, permitting the full charge packet to advance along another electrode path. Consequently, when a diminished charge packet having an assigned binary value is applied to the regenerator circuit, a full charge packet representing the same binary value is transferred out, and without inversion. In the absence of a charge packet at the binary input indicating the alternate binary value, the unitary charge under the storage electrode is directed out the shunt path. Advantageous arrangements are provided for in-line transfer of the data signal, sequential advance of the charge packets and dissipation of charge residues. By appropriate use of additional input transfer gates and output transfer gates, the regenerator circuit serves as a basic unit which can provide fundamental logical and digital functions needed in digital systems, including OR gates, AND gates, EXCLUSIVE-OR gates, half adders and full adders.