Microprocessor controlled CRT display system
A display system is disclosed wherein a refresh memory is divided into a plurality of blocks of bytes so that a micro-processor can access the blocks byte by byte while display data of the plurality of blocks are assembled by word so that the display data are accessed word by word. The access by the...
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creator | HAMADA NAGAHARU |
description | A display system is disclosed wherein a refresh memory is divided into a plurality of blocks of bytes so that a micro-processor can access the blocks byte by byte while display data of the plurality of blocks are assembled by word so that the display data are accessed word by word. The access by the micro-processor and the access for display are time-shared at a timing of one half of one character display to avoid wait time for the accessing. |
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The access by the micro-processor and the access for display are time-shared at a timing of one half of one character display to avoid wait time for the accessing.</description><language>eng</language><subject>ADVERTISING ; ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION ; CALCULATING ; COMPUTING ; COUNTING ; CRYPTOGRAPHY ; DISPLAY ; EDUCATION ; ELECTRIC DIGITAL DATA PROCESSING ; IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ; PHYSICS ; SEALS</subject><creationdate>1978</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19780801&DB=EPODOC&CC=US&NR=4104624A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19780801&DB=EPODOC&CC=US&NR=4104624A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HAMADA; NAGAHARU</creatorcontrib><title>Microprocessor controlled CRT display system</title><description>A display system is disclosed wherein a refresh memory is divided into a plurality of blocks of bytes so that a micro-processor can access the blocks byte by byte while display data of the plurality of blocks are assembled by word so that the display data are accessed word by word. The access by the micro-processor and the access for display are time-shared at a timing of one half of one character display to avoid wait time for the accessing.</description><subject>ADVERTISING</subject><subject>ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>CRYPTOGRAPHY</subject><subject>DISPLAY</subject><subject>EDUCATION</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>IMAGE DATA PROCESSING OR GENERATION, IN GENERAL</subject><subject>PHYSICS</subject><subject>SEALS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1978</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNDxzUwuyi8oyk9OLS7OL1JIzs8rKcrPyUlNUXAOClFIySwuyEmsVCiuLC5JzeVhYE1LzClO5YXS3Azybq4hzh66qQX58anFBYnJqXmpJfGhwSaGBiZmRiaOxoRVAAAkwSl7</recordid><startdate>19780801</startdate><enddate>19780801</enddate><creator>HAMADA; NAGAHARU</creator><scope>EVB</scope></search><sort><creationdate>19780801</creationdate><title>Microprocessor controlled CRT display system</title><author>HAMADA; NAGAHARU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US4104624A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1978</creationdate><topic>ADVERTISING</topic><topic>ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>CRYPTOGRAPHY</topic><topic>DISPLAY</topic><topic>EDUCATION</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>IMAGE DATA PROCESSING OR GENERATION, IN GENERAL</topic><topic>PHYSICS</topic><topic>SEALS</topic><toplevel>online_resources</toplevel><creatorcontrib>HAMADA; NAGAHARU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HAMADA; NAGAHARU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Microprocessor controlled CRT display system</title><date>1978-08-01</date><risdate>1978</risdate><abstract>A display system is disclosed wherein a refresh memory is divided into a plurality of blocks of bytes so that a micro-processor can access the blocks byte by byte while display data of the plurality of blocks are assembled by word so that the display data are accessed word by word. The access by the micro-processor and the access for display are time-shared at a timing of one half of one character display to avoid wait time for the accessing.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | ADVERTISING ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION CALCULATING COMPUTING COUNTING CRYPTOGRAPHY DISPLAY EDUCATION ELECTRIC DIGITAL DATA PROCESSING IMAGE DATA PROCESSING OR GENERATION, IN GENERAL PHYSICS SEALS |
title | Microprocessor controlled CRT display system |
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