Clock converter circuit

This invention discloses a structure whereby a fixed frequency machine clocking signal can be multiplied in frequency by any desired integral value. The device uses a tapped delay line having a total time delay slightly less than the time of one-half cycle of the clocking signal and an exclusive-OR tree connected to the taps of the delay line to generate a higher frequency output clock signal. By interposing a known frequency division network to the input of the delay line, the output clock signal can be generated with any desired rational relationship to the driving clocking signal.