Logical circuit with field effect transistors

An R-S flip-flop or a binary frequency divider comprises at least one logical gate controlled by the state of variables taking one of two values neighboring the voltages at positive and negative terminals of a voltage source. The output node associated with said gate is connected to said negative terminal by a first group of n-channel field effect transistors and to said positive terminal by a second group of n-channel field effect transistors. The voltage state at said node is determined by the states of conduction of the associated first and second groups of transistors, in such a way the simultaneous blocking of the first and second groups of transistors associated with one gate is provided for at least one combination of input variables.