INTEGRATED THRESHOLD MNOS MEMORY WITH DECODER AND OPERATING SEQUENCE

A digital memory system employing a rectangular array of known MNOS variable threshold insulated gate field effect transistor memory cells is actuated by auxiliary circuits which provide a four-step operating sequence. The memory cells are arranged in word rows in which the gate electrodes of all memory cells in a given row are connected together and in bit columns having common source and common drain connections. The auxiliary circuits provide intermediate gate voltages to a selected row of memory cells in the first step of the operating cycle so as to read the information stored in the memory cells into a register. In the second step of the operating sequence, a large negative gate voltage is applied to the selected row to circumvent the cumulative effect that might arise from a succession of positive WRITE pulses. In the third operating step, the memory cells in the selected row are set to their least negative threshold value by an appropriate "clear" pulse, and in the fourth operating step information is written back into the selected memory cells from the register.