SYNCHRONIZED STATIC MOSFET LATCH

1414217 Bistable circuits INTERNATIONAL BUSINESS MACHINES CORP 31 Aug 1973 [28 Sept 1972] 41108/73 Heading H3T A two-phase latch circuit comprises a capacitive input stage 31-35 including an FET circuit 31 or 32 responsive to clock signals # 1 of a first phase for storing at 34, 35 a set or reset input information, an output stage comprising a two state circuit 13 including a pair of cross-coupled FETs 15, 151, and an FET circuit 33, 36, 37 responsive to clock signals # 2 of a second phase to switch the two state circuit to a state corresponding to whether a set or reset information is being stored. In operation, the set input is gated at 31 by the # 1 clock pulses and stored at 35. Subsequently when the # 2 clock pulses appear, the line 38 is connected to ground via FETs 36, 33 and the capacitor 35 also discharges via the conducting FETs. The reset operation functions in a similar manner.