DATA PROCESSING SYSTEM HAVING AUTOMATIC INTERRUPT IDENTIFICATION TECHNIQUE

A plurality of devices are coupled with a data processor over a common electrical bus. Each device makes its own interrupt request which is not seen by the processor until a request enable signal is generated therefrom. In response to the enable signal, the interrupt requesting device of highest priority provides its device address or identification to the processor. The device address which is independent of the type of the device, i.e., magnetic tape, disk, or teletype, etc., is augmented with a memory table base address in order to address the interrupt service routine for the interrupting device. The highest priority device is indicated by a priority network which in combination with the interrupt logic of each device, allows the devices to arbitrate amongst themselves, without the knowledge of the processor, to determine which device is to send its device address to the processor.