DESKEWING BUFFER ARRANGEMENT WHICH INCLUDES MEANS FOR DETECTING AND CORRECTING CHANNEL ERRORS

A deskewing buffer system includes a plurality of storage registers each of which include a plurality of storage devices. Pairs of the storage devices provide storage for a single information channel. The devices of each channel further includes circuits for detecting when no information has been stored by an input pair of storage devices of a channel within a bit interval which signals a dropped bit within the channel. The detection circuits are then operative to switch both input storage devices of the channel to the same predetermined state. Thereafter, checking circuits coupled to a last register of the buffer system are operative to check the deskewed contents of the register and generate a signal indicating whether the channel dropped a binary ONE or binary ZERO bit. The signal is then used to transfer selectively the state of one of the pairs of storage devices of the channel to an output register.