CLOCK APPARATUS AND DATA PROCESSING SYSTEM

Disclosed is a clock apparatus for use in a data processing system. The clock pulse width is made substantially equal to the maximum latch delay (MLD) plus the clock skew (CS) for obtaining the minimum number of circuits relative to the maximum clock frequency.

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Bibliographische Detailangaben
1. Verfasser:	GRANT G,US
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY HANDLING RECORD CARRIERS IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS PHYSICS PRESENTATION OF DATA PULSE TECHNIQUE RECOGNITION OF DATA RECORD CARRIERS RESONATORS
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Beschreibung
Zusammenfassung:	Disclosed is a clock apparatus for use in a data processing system. The clock pulse width is made substantially equal to the maximum latch delay (MLD) plus the clock skew (CS) for obtaining the minimum number of circuits relative to the maximum clock frequency.