METHOD OF TESTING MOSFET PLANAR BOARDS

A technique of testing a MOSFET planar board in which each of the chips on the planar board can be electronically isolated for individual testing. In MOSFET technology there are two off chip inverters between the output logic blocks and the pins. These are the preoff chip inverter and the off chip inverter. A NOR gate is formed by adding an additional input line to each of the preoff chip inverters of each of the chips on the board, and the output of each of the chips which are not to be tested are driven to logical ones by application of a positive logical level to this input line while no input is applied to the NOR gates on the outputs of the chip which is to be tested. In this manner, all inputs to the chip to be tested are at a one or high logical level, and for test purposes each input to the chip can be brought to a low logical level or left at a high logical level in accordance with the test pattern to be applied. Its output or reaction to the input test patterns is monitored in the normal manner by the chip tester. Through utilization of this technique, the same test patterns which might number three thousand can be applied to the chip such that even though it remains on the planar board it can be tested equivalent to new. In this manner, each chip can be tested and a defective chip on a planar board isolated without mechanically isolating the chips by breaking chip interconnections.