DATA PROCESSING SYSTEM INCLUDING A SMALL AUXILIARY PROCESSOR FOR OVERCOMING THE EFFECTS OF FAULTY HARDWARE

An electronic data processing system comprising a relatively large main processor, a relatively small auxiliary processor, and a bus system linking both of said processors. The auxiliary processor is linked, via the bus system, to various portions of the main processor including data registers, error checking circuits, and function decoders. If one of the error checking circuits within the main processor detects a machine malfunction, the auxiliary processor will be able, via the bus system, to determine the portion of the main processor in which the malfunction occurred (by detecting which error check circuit detected the malfunction), and to determine the function which the main processor was attempting to perform when the malfunction occurred (by examining the output of the function decoder). The auxiliary processor will then, also via the bus system, address a data register which furnished input data to the failing portion of the main processor and extract the data therefrom; the auxiliary processor will manipulate the data (in accordance with the function defined by the function decoder in the main processor) to produce the result that would have been produced if the malfunction had not occurred (thereby, in effect, simulating the malfunctioning portion of the main processor); and, again via the bus system, the auxiliary processor will transmit the result to a data register within the main processor which accepts output data from said failing portion. The main processor will then be restarted to continue processing.