LOW POWER FET DRIVER CIRCUIT

Disclosed is an FET (field effect transistor) driver circuit capable of driving large capacitive loads, while dissipating relatively little power. A delay circuit forms a parallel path between the circuit input and output providing a delayed signal at the output of the circuit after the gate to source feedback capacitor of the output FET has been charged. The particular delay circuit disclosed herein accurately tracks the driver circuit providing a precise time delay for limiting transient power dissipation in high frequency operation.