FET DYNAMIC LOGIC CIRCUIT AND LAYOUT

An MOS FET dynamic logic system includes six clock phase inputs. Interconnected FET logic curcuit stages are formed on a wafer substrate upon which plural parallel columns or stacks of diffusions have been placed. Generally, transverse metallization overlies the diffusions and usually crosses them at right angles with three clock lines crossing each set of diffusions. Successive stages are interconnected based upon rules which define phase relationships which are permissible for providing valid logic operations. Only one of a cyclically operating sequence of phase defining clocks is connected to each stage.