FET ADDRESS DECODER

This specification described a logic circuit having a capacitor coupled between the gate and the drain of an FET. The capacitor used is a polarized voltage dependent capacitor and the voltage across this capacitor is controlled to render the FET conductive or nonconductive to selectively gate or not gate pulses applied to the drain of the FET through the FET to a load connected to the source of the FET. When signals are not to be gated through the FET the voltage across the capacitor is maintained at zero potential and the capacitor exhibits substantially zero capacitance. When signals are to be gated through the FET a voltage of a particular potential and polarity is maintained across the capacitor so that the capacitor exhibits a high capacitance. In operation this logic circuit does not form a significant load on the source of potential driving it when the FET is gated nonconductive.