ERROR CHECKING ARRANGEMENT

ERROR CHECKING ARRANGEMENT

This disclosure is for a rearrangement of the input/output controls of a small central processing unit (CPU) to enable interspersed use of the input/output devices by the CPU and by the customer engineer. This configuration allows the engineer to read the status of the devices and to test their func...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: LEOPOLD REICHL, HERMANN WEBER, ROBERT VACHENAUER, FRITZ KOEDERITZ, HELMUT PAINKE, EDWIN VOGT, GUNTER KNAUFT, HANS H. LAMPE
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:This disclosure is for a rearrangement of the input/output controls of a small central processing unit (CPU) to enable interspersed use of the input/output devices by the CPU and by the customer engineer. This configuration allows the engineer to read the status of the devices and to test their functions without interference with the CPU usage of the devices and without shutting down of the system.