SYNCHRONOUS TIMING SYSTEM HAVING FAILURE DETECTION FEATURE

1296064 Selective signalling WESTING- HOUSE ELECTRIC CORP 27 Aug 1969 [26 Sept 1968] 42704/69 Heading G4H A synchronization waveform 5A1, Fig. 5, is supplied over line 14 to counters 18 at remote stations, the waveform containing a pulse in as many time slots as there are stations and an empty, synchronizing time slot which is detected at 24 to reset the counters 18. Information 5A3 transmitted over line 16 is sampled and held by a bi-stable circuit 22 at each station which is enabled by counter 18 and gate 20 during the corresponding time slot, each time slot including an information bit pertaining to the enabled station. The information is preferably in a "comma-free" code so that if the reset of a counter fails the counter will precess and the resulting randomized data sampled will be indicative of a loss of synchronism. Alternatively, if speech is transmitted in time division multiplex, loss of synchronism will be indicated by an unintelligible output. The reset circuit includes an AND gate which receives inputs from the synchronization waveform and from a circuit tuned to that waveform frequency, the inputs being similar only during the synchronizing time slot.