SERIAL LOOP DATA TRANSMISSION SYSTEM FAULT LOCATOR

1,247,657. Signalling between a central and remote stations; computer input - output. INTERNATIONAL BUSINESS MACHINES CORP. 9 April, 1970 [30 April, 1969], No. 16824/70. Headings G4A and G4H. In a communication system of the kind in which a central station and a series of remote stations are connected in series in a loop, means are provided for locating a fault comprising means for indicating a fault and means responsive to the fault indication for transmitting on the loop a predetermined signal, a part of which identifies the address of the remote station, and means for preventing the remote station from transmitting a signal identifying its address on reception of a predetermined signal indicating a fault in any of the preceding stations on the loop. Fig. 4 shows a remote station. Data is received from the previous remote station on twisted leads 21 at the left-hand side and sent out on leads 21 on the right to the next remote station. The incoming pulses are grouped in bytes of 8 bits as shown in Fig. 2 which illustrates a single " channel." The first byte contains a start code, the second the address of one of the remote stations, the third the address of one of the terminal devices at that station, the fourth defines a control to be performed, the fifth contains data, e.g. to operate a printer and the following 25 bytes are used for synchronization. The groups relating to successive channels are sent in a predetermined sequence. The binary bits are sent as signals of opposite polarity. At a remote station, Fig. 4, the pulses are applied via OR gate 23 to circuit 24 which extracts the data and passes it to the shift register 25 and to " data present tester " 40. Clock pulses are derived and used to shift the data into the shift register 25 and to enable gate 20 to gate the data out to the next station. Counter 28 counts the clock pulses and gives successive outputs on eight leads, the first lead is connected to step a byte counter 30 having outputs on 5 leads. Counters 28 and 30 are reset by signals from gates 29, 31. Circuit 33 receives data from the shift register 25, a " data sample " signal from circuit 24, outputs 4-8 from counter 28 and a signal, inverted at 34, indicating that byte synchronism has been lost. When the signal from inverter 34 disappears, circuit 33 gives a fault output. This output is applied to gate 36 with the " load clock" signal of circuit 24 and the 8 output of counter 28. The output of this gate enters data from bus 38 into