MONOLITHIC CIRCUIT MANUFACTURE AND PHOTORESIST EXPOSURE TECHNIQUE UTILIZED THEREIN

1,191,106. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORP. 4 Oct., 1967 [16 Nov., 1966], No. 45182/67. Heading H1K. [Also in Division G2] A monolithic integrated circuit semi-conductor wafer W is tested (Fig. 1, not shown), by a known system to determine the acceptable network components thereof, and the data so obtained is used to control apparatus for exposing a photo-resist coating on the wafer W so as to form thereon a wiring interconnection pattern linking only the acceptable components. The data is fed to a computer 17 which determines the wiring interconnection pattern to be formed and generates instructions to this effect. These cause a glass plate 21 to be pivoted about by servomotors 19, 20, each controlling rotation about one of a pair of orthogonal axes. Movement of the plate 21 varies the point of impingement of a narrow light beam 22 on the wafer W, since the beam is refracted and hence displaced by differing amounts as the plate moves. The wafer is attached to a support which can be moved when no more of the circuit can be formed by tilting the plate 21. A third servomotor 90 controls a shutter 89 which is closed while the wafer position is adjusted. A modified light source (Fig. 12, not shown) emitting a plurality of collimated light beams for tracing simultaneously a plurality of identical latent images may be used instead of the source 23 which emits the single beam 22. Instead of utilizing the apparatus to expose the wafer directly, it may be used to expose a photographic film from which a mask, later used to expose the wafer, may be made. The wafer W is coated with a metallic layer and with a photo-resist coating, which coating is exposed as described above to form a latent image. The photo-resist coating is then developed, the unexposed portions being removed, and an etchant then applied to remove those portions of the metallic layer not protected by the developed image. Finally, the developed image is removed to leave the wiring interconnection pattern on the wafer.