Print read-out in computer systems using stored programs

909,784. Electronic computer programmes. NATIONAL CASH REGISTER CO. Dec. 13, 1960 [Dec. 15, 1959], No. 35054/61. Divided out of 909,781. Class 106(1). Two sections of an instruction register store respective operand addresses and in response to a predetermined instruction the same operation is performed on a plurality of pairs of operands, the first and second members of the pairs being stored in a first and second series of adjacent storage locations respectively. In the example an instruction APN entered into section I1 of the instruction register requires that the numbers in the addresses specified in sections I3, I4 should be added. If the number in section I2 is greater than 1 then the addresses in I3 and I4 are respectively incremented and decremented and the process repeated. At the end of the operation the address of the succeeding instruction is found in section I5. Detailed operation. The number in section I1 is entered into control circuit N, and the number (units digit only) in section I2 into reverse counter RC. The magnetic core memory M is of the type described more fully in Specification 909,781, in which 10-decimal-digit words can be stored in each of the rows 0-99 of the main register. An additional row A can store an intermediate result. A row or Y-conductor is selected by the energization of one Y-driver YD and one Y-grounder YG under the control of tens and units counters WH, WL. A bit or X-conductor is likewise selected by XG and XD under the control of 4-bit and decimal counters BC, DC. Sense conductors SA, SM are threaded, respectively, through all the A and main memory cores. The number in section I3 selects an address from which the stored word is transferred to section A in serial manner with appropriately sequential operation of BC and DC. Section I4 then selects the address of the second operand. The lowest decimal digits from this address and the register A are then transferred to registers J and K. J and K are connected to a parallel adder-subtractor A/S which stores the sum digit and the carry bit. The sum digit is recorded in A and the process repeated for successive decimal digits with allowance for the carry from the lower denomination. At the end of the addition the sum is recorded in the second specified address. The count in section I3 is increased by 1, that in RC and I4 decreased by 1 and the process repeats. When RC is reduced to zero the process stops and the number stored in 15 is used to select the next instructi