Digital differential analyzers
799,667. Digital electric calculating-apparatus. BENDIX AVIATION CORPORATION. Oct. 21, 1954 [Nov. 6, 1953], No. 30356/54. Class 106 (1). In a digital calculator for integration and differential analysis comprising a set of storage sections, common computer means arranged to coact with each section t...
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Zusammenfassung: | 799,667. Digital electric calculating-apparatus. BENDIX AVIATION CORPORATION. Oct. 21, 1954 [Nov. 6, 1953], No. 30356/54. Class 106 (1). In a digital calculator for integration and differential analysis comprising a set of storage sections, common computer means arranged to coact with each section to perform a fixed sequence of operations whereby in response to first and second input trains of pulses representing increments of an integrand variable (y) and a variable of integration (x) respectively, an output train of pulses is produced such that its effective rate at any time corresponds to the product of a number (y) cumulated from the pulses in the first train with the effective rate of the pulses in the second train, and means whereby the output train can be introduced as the first or second input train for one or more selected storage sections, partial corrective terms corresponding to successive increments of y are cumulated and stored for each section until the occurrence of a pulse representing an increment of x when the computer means algebraically adds the total cumulated value of the corrective terms to y, the cumulation and storage of the corrective terms then being resumed from zero. The computer described is generally similar to that of Specification 748,267 and includes a magnetic drum having in addition to the Y, R and clock pulse channels 14, 16 and 24, Fig. 1, two information precessing Z channels 20, 22 for indicating respectively the existence and polarity of y #x increments, and a further channel 18 containing corrective values corresponding to ¢ #y (where #x, #y represent increments in x, y respectively). Three similar read, erase and record coils, e.g. 26, 28 and 30, are provided for each of the channels 14, 16, 18, 20, 22. Channel 14, 16, 18 are divided into 22 successive integrator member sections I 1 -I 22 each the length of 48 clock pulses P 1 -P 48 , the pulse times and intervals I 2 -I 22 being marked off by clock pulse counters 60, 62 respectively. Simplified embodiment. The computing circuits, shown in simplified form in Fig. 1, comprise, as well as counters 60, 62, three sections described separately below: (i) a y-loop; (ii) a loop for cumulating the corrective terms ¢ #y; (iii) an integraing loop. (i) y-loop. The #y code pulses in positions P 1 -P 22 of a given memory section on channel 14, recirculated via gate 64, are fed to a gate circuit 72. Provided a code pulse coincides with a pulse from channel 20, a unit is added |
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