DECODING METHOD, PROCESSOR, CHIP, AND ELECTRONIC DEVICE

Embodiments of the present disclosure provide a decoding method, a processor, a chip, and an electronic device. The method includes: generating an instruction fetch request carrying at least one switching flag, in which the switch tag at least indicates an instruction position for performing decoder group switch; acquiring an instruction stream fetched by the instruction fetching request in response to a micro-op being obtained as decoded by decoder group, and determining the instruction position for performing decoder group switch in the instruction stream according to the switch tag carried by the instruction fetching request; allocating the instruction steam to a plurality of decoder groups for parallel decoding according to the instruction position; and attaching the switch tag to a target micro-op obtained by decoding a targe instruction, in which the target instruction is an instruction corresponding to the instruction position.