MECHANISM FOR EFFICIENT MASSIVELY-CONCURRENT CONDITIONAL COMPUTATION

According to embodiments of the present disclosure, processor chips adapted for efficient massively-concurrent conditional computation are provided. In various embodiments, a chip comprises at least one processing core; a controller operatively coupled to the at least one processing core; and an instruction memory in communication with the controller. The controller is configured to: concurrently compute a plurality of relational operators on a plurality of inputs, resulting in a plurality of results; combine the plurality of results to determine an index; select an operation based on the index; and cause the at least one processing core to execute the selected operation.