CRYPTOSYSTEM WITH UTILIZING SPLIT-RADIX DISCRETE GALOIS TRANSFORMATION

A cryptosystem processor includes a twiddle factor memory, a SRDGT BFU, and a SPN. The twiddle factor memory has ZETA ports. The at least one SRDGT BFU has six input ports and four output ports and switchable among operation in DGT/IDGT/CWM mode, in which two of the input ports electrically communicate with the ZETA ports, respectively. The SRDGT BFU is configured to read and write two data points when working under the DGT/IDGT mode and is configured to read and write four data points when working under the CWM mode. The SPN electrically communicates with the SRDGT BFU and has at least one dual-port BRAM serving as memory cache configured to store polynomial, in which the SPN is configured to support the required number of data points reading or writing per cycle in the DGT/IDGT/CWM mode.