NEURAL NETWORK COMPUTATION CIRCUIT, CONTROL CIRCUIT THEREFOR, AND CONTROL METHOD THEREFOR

A neural network computation circuit includes: a plurality of word lines; a plurality of memory cells; a word-line drive circuit; a column selection circuit; a computation circuit that performs neuron computation; a word-line selected-state signal generation circuit; a timing generation circuit; a computation-result processing circuit; and a selected word-line count management circuit that manages a selected word-line count that is information relevant to a total number of word lines that are placed in a selected state when a multiply-accumulate operation is performed, and transmits the selected word-line count to the timing generation circuit. The timing generation circuit sets, according to the selected word-line count, a delay time from when a word-line activation signal is output until when a computation-circuit control signal is output.