MULTIPLIER WITH IN-PATH SUBNORMAL HANDLING

A multiplier with in-path subnormal handling includes a zero counter, a multiplication circuit, a comparator and a rounder. The zero counter receives a first mantissa and a second mantissa, and output a zero count by adding up a first trailing-zero count, a second trailing-zero count, and at least one of a first leading-zero count and a second leading-zero count. The multiplication circuit outputs a mantissa product by multiplying the first mantissa and the second mantissa. The comparator outputs a sticky bit by comparing the zero count and a sticky portion width varying according to the most significant bit of the mantissa product. The rounder outputs a mantissa result by performing a rounding operation according to the mantissa product and the sticky bit.