FLOATING DATA LINE CIRCUIT AND METHOD

A memory circuit includes first and second write lines and memory segments. A first driver includes, between power and reference nodes, a PMOS transistor and a first inverter including an input coupled to a first driver first input and an output coupled to the first write line, and a second inverter coupled between the PMOS transistor gate and a first driver second input. A second driver includes, between the power and reference nodes, a PMOS transistor and a third inverter including an input coupled to a second driver first input and an output coupled to the second write line, and a fourth inverter coupled between the PMOS transistor gate and a second driver second input. Each of the first driver first input and second driver second input receives a first data signal, and each of the first driver second input and second driver first input receives a second data signal.