NANOWIRE TRANSISTOR FABRICATION WITH HARDMASK LAYERS

A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those...

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Bibliographische Detailangaben
Hauptverfasser:	Sung, Seung Hoon, Rachmady, Willy, Kim, Seiyon, Kavalieros, Jack T, Kuhn, Kelin J
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY LINING MACHINES MATERIALS FOR SURFACES USED IN PRINTING MACHINES FOR PRINTING,INKING, DAMPING, OR THE LIKE PERFORMING OPERATIONS PREPARING SUCH SURFACES FOR USE AND CONSERVING THEM PRINTING PRINTING MACHINES OR PRESSES PRINTING PLATES OR FOILS SEMICONDUCTOR DEVICES STAMPS TRANSPORTING TYPEWRITERS
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Beschreibung
Zusammenfassung:	A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.