MULTI-THRESHOLD VOLTAGE INTEGRATION SCHEME FOR COMPLEMENTARY FIELD EFFECT TRANSISTORS

Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices, e.g., complementary field-effect transistors (CFETs) that meet reduced thickness, reduced leakage, lower thermal budget, and Vt requirements (including multi-Vt), and have improved device performance and reliability. Some embodiments of the methods include conventional dipole engineering techniques such as dipole first processes and/or dipole last processes without the need for repairing the interfacial layer after treatment (in dipole first processes) or repairing the high-K dielectric layer after the annealing process (in dipole last processes).