TIMING ANALYSIS FOR NON-SCAN LATCHES

TIMING ANALYSIS FOR NON-SCAN LATCHES

The present disclosure describes systems and methods for performing timing analysis of circuit designs. According to an embodiment, a method includes assigning a timing margin to a non-scan latch of a circuit design and performing a timing analysis on the circuit design using the timing margin for t...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: ALLEN, Robert John, RAO, Rahul M, GUPTA, Hemlata, WOOD, Michael Hemsley, FOREMAN, Eric, RAJASHEKARA, Karthik, KALAFALA, Kerim, BUCK, Nathan, KO, Tsz-Mei, DEDRICK, Daniel
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:The present disclosure describes systems and methods for performing timing analysis of circuit designs. According to an embodiment, a method includes assigning a timing margin to a non-scan latch of a circuit design and performing a timing analysis on the circuit design using the timing margin for the non-scan latch to produce timing results for the circuit design. The timing results include a slack value. The method also includes calculating a credit based on the slack value and updating the slack value based on the credit.