TRANSISTOR STRUCTURE AND METHODS OF FORMATION

A medium voltage transistor of a level shifter circuit may include a p-well region in a substrate. Moreover, the medium voltage transistor may include an n-type lightly-doped source/drain (NLDD) region in which an N+ source/drain region of the medium voltage transistor is included. The light doping in the NLDD region enables a threshold voltage (Vi) to be reduced while enabling medium voltage operation at the N+ source/drain region. To reduce the amount of current leakage in the medium voltage transistor due to the light doping in the NLDD region, a buffer layer may be included over and/or on a portion of the NLDD region under a gate structure of the medium voltage transistor. The NLDD region and the thermal region of the medium voltage transistor enables the threshold voltage of the medium voltage transistor while maintaining the same current leakage performance or reducing current leakage in the medium voltage transistor.