ROUNDING IN FLOATING POINT ARITHMETIC

An apparatus, a computer-readable medium, a system, a chip-containing product and a method are provided relating to floating point arithmetic, wherein a combined arithmetic operation with respect to three input floating point values is performed. The combined arithmetic operation comprises a rounded first arithmetic operation on the first and second input floating point values generating a rounded first arithmetic result and a rounded second arithmetic operation on the rounded first arithmetic result and the third input floating point value to generate a final rounded result of the combined arithmetic operation. When a shift operation on a non-zero mantissa of the third input floating point value generates a zero-value shifted mantissa, the zero-value shifted mantissa is adjusted to become non-zero.