SEMICONDUCTOR DEVICE INCLUDING VERTICAL ROUTING STRUCTURE AND METHOD FOR MANUFACURING THE SAME

A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extend...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: LIN, Chung-Te, WEN, Wei-Chih, TSAI, Han-Ting
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.